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http://www.cirrus.com copyright ? cirrus logic, inc. 2007 (all rights reserved) 2 x 15 w cs4525 digital amplifier reference design features ? output filters optimized for 8 loads ? delivers 15 w/ch into 8 at 0.5 % thd+n ? single-ended 2 v rms stereo analog inputs ? optical and coaxial s/pdif inputs ? demonstrates emi compliant design per fcc class b part 15 and cispr 22 standards ? flexible i/o headers provided ? pcm input signal interface ? auxiliary serial po rt signal interface ? delay port signal interface ? pwm logic level signal interface ? optional crd4412a daughter-card for subwoofer channel ? implements a 2.1 configuration ? demonstrates recommended 4-layer layout and grounding arrangements ? +18 v switching mode power supply included ? can be operated by on-board controls or with windows ? compatible graphical user interface description the crd4525-q1 demonstrates the cs4525 digital pwm controller with integrated power stages. this ref- erence design implements a two-channel amplifier that delivers 15 w per full-bridge channel into 8 loads us- ing a single +18 v supply. the crd4525-q1 is powered by an included 80 w switching mode power supply. standard rca phono jacks are provided to easily inter- face analog input signals with the evaluation board. optical and coaxial inputs are provided to interface with s/pdif digital audio input signals. the pwm audio power outputs are routed through an inductor/capacitor 2 nd order low-pass filter (lpf) to re- move high-frequency components from the output signal, effectively converting it from digital to analog. the windows software provides a gui to make config- uration of the crd4525-q1 easy. the software communicates through the pc?s usb port to configure the control port registers so that all features of the cs4525 can be evaluated. additionally, control over ba- sic functions is possible via on-board hardware controls without the need to attach the crd4525-q1 to a pc. ordering information crd4525-q1 cs4525 reference design cs4525 stereo analog inputs optical receiver output filter speaker connector coaxial input cs8416 s/pidf receiver pcm input header usb i/o micro-controller status led?s tactile controls aux port header crd4412a interface header power jack included 18 v power supply 8 8 output filter crd4525-q1 october '07 ds804rd4
2 ds804rd4 crd4525-q1 table of contents 1. system overview ............................................................................................................ ................. 4 1.1 power ..................................................................................................................... .......................... 4 1.2 cs4525 digital amplifier ............................. ..................................................................... ................ 4 1.3 cs8416 digital audio receiver ............................................................................................. ........... 4 1.4 system clocking ........................................................................................................... ................... 4 1.5 external data headers ..................................................................................................... ................ 4 1.6 analog inputs ............................................................................................................. ...................... 5 1.7 speaker outputs ........................................................................................................... ................... 5 1.8 pc control ................................................................................................................ ....................... 5 1.9 stand-alone control ....................................................................................................... .................. 5 1.10 external power stage interface ................ ........................................................................... .......... 6 2. pc software control ........................................................................................................ ........... 7 2.1 cs4525 main controls tab .................................................................................................. ............ 7 2.2 cs4525 aux & filter controls tab .......................................................................................... ......... 8 2.3 s/pdif input controls tab ................................................................................................. .............. 9 2.4 register maps tab ......................................................................................................... ................ 10 2.5 pre-configured script files ............................................................................................... ............. 11 2.5.1 analog in ............................................................................................................... ................ 11 2.5.2 optical spdif in ........................................................................................................ ............ 11 2.5.3 coaxial spdif in ........................................................................................................ ........... 11 3. stand-alone mode control ................................................................................................... .. 12 4. grounding and power supply decoupling ........................................................................ 12 4.1 power supply decoupling .... ............................................................................................... ........... 12 4.2 electromagnetic interference (emi) ........................................................................................ ....... 12 4.2.1 suppression of emi at the source ........................................................................................ .13 5. system connections & jumpers .............................................................................................. 1 4 6. crd schematics ............................................................................................................. ................. 15 7. crd layout ................................................................................................................ ...................... 18 8. performance plots .......................................................................................................... ........... 23 9. thermal de-rating .......................................................................................................... .............. 29 10. electromagnetic compliance (emc) performance ...................................................... 30 10.1 emi testing procedures ................................................................................................... ........... 30 10.2 system configuration ..................................................................................................... .............. 31 10.3 crd4525-q1 test results .................................................................................................. ........ 31 11. revision history .......................................................................................................... ................ 32 list of figures figure 1.speaker terminal configuration .......... ............................................................................. ............ 5 figure 2.cs4525 main controls tab ............................................................................................. .............. 7 figure 3.cs4525 aux & filter controls tab .... ................................................................................. ........... 8 figure 4.s/pdif input controls tab ............................................................................................ ................ 9 figure 5.register maps tab .................................................................................................... .................. 10 figure 6.cs4525 - schematic page 1 ............................................................................................ ........... 15 figure 7.usb microcontroller & tactile control - schem atic page 2 ........................................................ 16 figure 8.power & i/o connections - schematic page 3 ........................................................................... 17 figure 9.component map ........................................................................................................ ................. 18 figure 10.top-side copper layer ...................... ......................................................................... .............. 19 figure 11.inner copper layer 1 ................................................................................................ ................ 20 figure 12.inner copper layer 2 ................................................................................................ ................ 21 figure 13.bottom-side copper layer ............................................................................................ ........... 22 figure 14.frequency response .................................................................................................. .............. 23 figure 15.thd+n vs. power ..................................................................................................... ................ 24
ds804rd4 3 crd4525-q1 figure 16.thd+n vs. frequency ................................................................................................. ............. 25 figure 17.fft at -60 db input .................................................................................................. ................. 26 figure 18.fft at 0 db input .................................................................................................... .................. 27 figure 19.inter-mod ulation distortion of 19 khz + 20 khz ...................................................................... .. 28 figure 20.thermal de-rating curve fo r a typical crd4525-q1 .............................................................. 29 figure 21.test facility setup ................................................................................................. ................... 30 figure 22.vertical peak scan data for the crd4525-q1 ......................................................................... 3 1 figure 23.horizontal peak scan data for the crd4525-q1 ..................................................................... 31 list of tables table 1. system connections ................................................................................................... ................ 14 table 2. on-board tactile contro ls ............................................................................................ ............... 14 table 3. system headers ....................................................................................................... ................... 14
4 ds804rd4 crd4525-q1 1. system overview the crd4525-q1 reference design is an excellent means fo r evaluating the cs4525 30 w digital amplifier with in- tegrated adc. analog and digital audi o input signal interfaces are provided ; an on-board microcontroller and usb pc interface is used for easily configuring the cs4525?s internal registers, and stand-alone mode is supported through on-board tactile controls. the crd4525-q1 schematic set is shown in figure 6 through figure 8 . 1.1 power a 80 w oem switching-mode power supply is included to power the crd4525-q1. the power supply pro- vides +18 v to the cs4525 power stages, and an on-board buck-converter and regulator provide power to the logic-level digital circuitry. power may be supplied from the included power suppl y or any 12-18 vdc power supply capable of deliv- ering sufficient current for the intended power output. connection for the power supply is provided in j3 (see the system connections table on page 14 ). 1.2 cs4525 digital amplifier a complete description of the cs4525 is included in the cs4525 product data sheet. optional user configuration settings of the cs4525 are pr ovided through its control port registers, accessible through the cs4525 tab of the cirrus logic flexgui soft ware. a register-level configuration interface is pro- vided on the register maps tab. see the ?pc software control? section on page 7 for more information. 1.3 cs8416 digita l audio receiver a complete description of the cs8416 receiver ( figure 8 on page 17 ) and a discussion of the digital audio interface are included in the cs8416 data sheet. the cs8416 converts the input s/pdif data stream into pcm data and clocks for the cs4525. the cs8416 operates in master mode and can provide pcm data in left-justified, i2s, right-justified 16-bit, and right- justified 24-bit interface formats. the most common operations of the cs8416 may be cont rolled via the s/pdif input controls tab in the gui software application. advanced options are accessible through the cs8416 sub-tab on the register maps tab of the cirrus lo gic flexgui software. 1.4 system clocking a 24.576 mhz parallel resonant crystal, y1, is available to provide a clock source to the cs4525. the crystal is mounted in pin sockets, allowing easy removal or replacement. alternatively, an input sys_clk signal can be provided on pin 3 of the serial audio input header (j2). 1.5 external data headers the evaluation board has been designed to allow interf acing with external systems via the headers j2, j4, and j11. figure 6 shows the headers? electrical connections. the 12-pin, 3 column header, j2, prov ides access to the cs4525?s seri al audio input and sys_clk input signals. place shunts across the sclk, lrck, and sd in pins located in the co lumns labeled ?s/pdif? to connect to the on-board s/pdif digital interface receiv er circuitry. to use an exte rnal digital audio source, simply remove the shunts and connect a ribbon across the sclk, lrck, and sdin pins located in the col-
ds804rd4 5 crd4525-q1 umns labeled ?ext sai?. a single ground column for the ribbon cable?s ground connection is provided to maintain signal integrity. the 8-pin, 2 column header, j11, provides access to the cs4525?s auxilia ry serial audio po rt output signals, as well as the sys_clk output signal . a single ground column is provid ed to maintain signal integrity. the 20-pin, 2 column header, j4, is included to interf ace with a crd4412a card. various signals, power, and ground are presented on this header. notably, this header includes the dly_sdout and dly_sdin signals which can be used to interface with an external delay device or dsp. see figure 6 for complete con- nectivity information. 1.6 analog inputs rca connectors supply the cs4525 analog inputs through single-ended passive circuits with one pole of input filtering. a resist ive attenuation network is implemented to allow 2 v rms input levels to be supplied to the crd4525-q1. refer to the cs4525 data sheet for the maximum input signal level at the analog input pins. 1.7 speaker outputs the cs4525 power outputs are configured for stereo full-bridge operation. the outputs are routed through a 2 nd order low-pass filter to remove high-frequency content from the output signals and then presented at the speaker wire crimp terminals (j5). th e output filters are optimized for 8 speaker loads. the speaker terminal connections are shown below. 1.8 pc control a usb connection is provided to facilitate softw are control of the cs452 5?s internal registers. a graphical user interface is available for the crd45 25-q1 to allow easy manipulation of the cs4525?s in- ternal registers. see the cs4525 data sheet for complete internal register descriptions. to enable the crd4525-q1, simply connect the suppli ed usb cable from an available usb port on a pc to the usb connector (j37) and launch the cirrus logic flexgui software. a visual indicator is provided by an on-board led (d12) that illuminate s when the board is being operated under pc control. when operating under pc control, the stand-alone controls on the board should not be manipulated. refer to ?pc software cont rol? on page 7 for a description of the graphical user interface (gui). 1.9 stand-alone control a volume control knob (s1), reset button (s2), and mute button (s3) are included for stand-alone operation of the crd4525-q1. these controls were not suppor ted by early versions of firmware running on the crd4525-q1, so it may be necessary to upgrade ol der firmware versions to enable their functionality. rl figure 1. speaker terminal configuration
6 ds804rd4 crd4525-q1 the on-board firmware can be upgraded by downloading and running the most recent version of the cirrus logic flexgui application. if necessary , this application (downloadable at www.cirrus.com/msasoftware ) will automatically upgrad e the firmware for an attached crd4525-q1 u pon start-up. 1.10 external power stage interface a keyed connector (j4) is included to interface with the crd4412a. the crd4525-q1 can be used with or without a crd4412a attached. without the crd4412a attached, the crd4525-q1 configur es itself for 2-channel stereo full-bridge opera- tion. when the crd4412a is attached, the cs4525 enables its bass manager and routes the lfe channel to the crd4412a which amplifies the signal in mono parallel full-bridge mode. together, the crd4525-q1 and crd4412a implement a 2.1 configuration. the crd4412a must be inserted and removed while power is not app lied to the crd4525-q1.
ds804rd4 7 crd4525-q1 2. pc software control the crd4525-q1 is designed for use with the microsoft ? windows-based flexgui grap hical user interface. this interface provides comprehensive control over the cs4525?s internal registers via a pc?s usb port. the flexgui software may be downloaded and installed from www.cirrus.com/msasoftware . step-by-step instructions for using the flexgui are provided as follows: 1. download and install th e flexgui software from www.cirrus.com/msasoftware . 2. connect the crd4525-q1 to a host pc using the supplied usb cable. 3. connect load speakers to the speaker output terminals. 4. connect an input source to the s/pdif or analog input connectors. 5. plug the input to the included +18 v power supply into an available power outlet. 6. plug the output of the included +18 v power supp ly into the power input connector on the crd4525-q1. 7. launch the flexgui software. the gui will load and be displayed. 8. un-check the ?power down cs4525? checkbox to power-up the device. in this state, the crd 4525-q1 will convert and amplify the content pres ent on the optical s/pdif input. 2.1 cs4525 main controls tab the cs4525 main controls tab provides a high-level, in tuitive interface to many of the basic configuration options of the cs4525. use this tab to access functions such as power-down, input source, and volume con- trol. figure 2. cs4525 main controls tab
8 ds804rd4 crd4525-q1 2.2 cs4525 aux & filter controls tab the cs4525 aux & filter controls tab provides a high-le vel, intuitive interface to many of the advanced con- figuration options of the cs4525. use this tab to configure the auxiliary port, the internal filters, and ad- vanced pwm adjustments. control over devi ce and board resets is also provided. the cs4525 parametric eq filter wizard, available for download from the cs4525 product page at www.cirrus.com , provides a graphical interface to the para metric equalization, bass manager, and tone control features of the cs4 525. using this utility, the user can graphica lly configure any or all of the five on- chip bi-quad filters, the bass manager crossover frequ ency, and the bass/treble shelving filters available in the cs4525. this utility creates a script file whic h can be loaded into the cs4525 utili zing the flexgui interface. please refer to cirrus logic application note an303 for more information regarding this valuable tool. figure 3. cs4525 aux & filter controls tab
ds804rd4 9 crd4525-q1 2.3 s/pdif input controls tab when the crd4525-q1 is configured to make use of the cs8416 s/pdif receiver, the devices must be configured for proper operation. t he s/pdif input controls tab provides a high-level, intuitive interface to the most common configurat ion options of the cs8416. figure 4. s/pdif input controls tab
10 ds804rd4 crd4525-q1 2.4 register maps tab the register maps tab provides an easy register-lev el interface to the on-board devices. register values can be modified on a bit-wise or byte-wise basis. to mo dify a single bit, first select the register by clicking its position in the register matrix; then click the a ppropriate push-button for the desired bit. to modify an entire register, simply enter the register?s new value directly into the register matrix. within the register maps tab, the cs4525 tab is used to access the cs4525?s internal registers, and the cs8416 tab is used to access the cs8416?s internal registers. figure 5. register maps tab
ds804rd4 11 crd4525-q1 2.5 pre-configured script files pre-configured script files are provided with the crd4525 -q1 to allow easy initial board bring-up. the board configurations stored within these files are described in sections 2.5.1 - 2.5.3 . 2.5.1 analog in using the pre-configured script file named ?analog in .fgs?, an analog input signal applied to the analog inputs of the crd4525-q1 will be used as the cs4 525?s input source. the de vice will be powered up with no internal processing active and the master volume control set to -20 db. 2.5.2 optical spdif in using the pre-configured sc ript file named ?optical spdif in.fgs? , the optical s/pdif input signal will be received by the cs8416 s/pdif receiver. the cs8416 pcm output signals will be used as the cs4525?s input source. the device will be pow ered up with no internal processi ng active and the master volume control set to -20 db. 2.5.3 coaxial spdif in using the pre-configured script file named ?coaxial spdif in.fgs?, the coaxial s/pdif input signal will be received by the cs8416 s/pdif receiver. the cs8416 pcm output signals will be used as the cs4525?s input source. the device will be pow ered up with no internal processi ng active and the master volume control set to -20 db.
12 ds804rd4 crd4525-q1 3. stand-alone mode control the crd4525-q1 is capable of operation without being connec ted to a computer by operating in stand-alone mode. when in this mode, the board is controlled by on-board hardware controls detailed in table 2 on page 14 .the rotary volume control on the edge of the board controls the vo lume. tapping the mute button mutes/un-mutes the pwm outputs of the cs4525. when a valid spdif signal is not presen t, the cs4525 is automatica lly configured to amplify the audio signal present on the rca analog input connectors. when a valid spdif si gnal is present, the cs4525 is automatically configured to amplify the audio signal present in the spdif stream . holding down the mute butt on for three seconds switches between optical spdif input and coaxial spdif input. 4. grounding and powe r supply decoupling the cs4525 requires careful attention to power supply and grounding arrangements to optimize performance and heat dissipation and mini mize radiated emissions. figure 9 on page 18 shows the component placement. figure 11 on page 20 shows the top layout. figure 13 on page 22 shows the bottom layout. the decoupling capacitors are located as close to the cs4525 as possi ble. extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise. 4.1 power supply decoupling proper power supply decoupling is one key to maximi zing the performance of a class-d amplifier. because the design uses an open loop outp ut stage, noise on the power supply rail will be coupled to the output. careful decoupling of the power st age supply rails is essential. figure 9 on page 18 demonstrates good de- coupling capacitor placement. notice that the small value decoupling capacitors are placed as close as physically possible to the power pins of the cs4525. the ground side of the capacitors is connected directly to top side ground plane, which is also used by the power supply return pins. this keeps the high frequency current loop small to minimize powe r supply variations and emi. 470 f electrolytic capacitors are also lo- cated in close proximity to the power supply pins to supply the current locally for each channel. these are not required to be expensive low-esr capacitors. genera l-purpose electrolytic capacitors that are specified to handle the ripple current can be used. 4.2 electromagnetic interference (emi) the emi challenges that face a maker of class-d amplif iers are largely the same challenges that have been faced by the switch mode power supply industry for many years. the numerous emi consulting firms that have arisen and the many books that have been written on the subject indicate the scope of potential prob- lems and available solutions. they should be considered a resource - most makers of switch mode equip- ment would benefit from developing a working relation ship with a qualified emi lab and from bringing their experience to bear on design issues, preferably early in the design process. this reference design is a board-level solution which is meant to control emissions by minimizing and sup- pressing them at the source, in contrast to containing them in an enclosure. the emi requirements for an amplifier have added dimensions beyond those imposed on power supplies. audio amplifiers are usually located in close proximity to radio receivers, particula rly am receivers which are notoriously sensitive to interference . amplifiers also need to operate with speaker leads of unpredictable length and construction which makes it possible for any high-frequency currents that appear on the outputs to generate nuisance emissions. for more detailed information regarding the emi pe rformance of the crd4525 -q1, please refer to section 10. ?electromagnetic compliance? on page 30 .
ds804rd4 13 crd4525-q1 4.2.1 suppression of emi at the source several techniques are used in the circuit design and boa rd layout to minimize high frequency fields in the immediate vicinity of the high power component s. specific techniques include the following: ? as mentioned in section 4.1 , effective power supply decoupling of high-frequency currents and mini- mizing the loop area of the decoupling lo op is one aspect of minimizing emi. ? each output of the cs4525 includes ?snubbing? components. for example, out1 includes snubber components r24 (5.62 ) and c23 (680 pf). these components serve to damp ringing on the switch- ing outputs in the 30-50 mhz range. the snubbing components should be as close as practical to the output pins to maximi ze their effectiveness. ? a separate ground plane with a solid electrical connection to the chassis, and which surrounds the speaker output connector, should be implemented. this allows the speaker outputs to be rf decou- pled to the chassis just before they exit the chassis from the speaker connector. ? make use of source termination resistors on all digital signals whose trac es are longer than about 25 mm.
14 ds804rd4 crd4525-q1 5. system connections & jumpers connector name reference designator signal direction connector function power in j3 input power connector. 12 to 18 vdc left in right in j1 j10 input analog input to cs4525 s/pidf input j6 input coaxial digital input to cs8416 s/pidf input j7 input optical digital input to cs8416 speaker connector j5 output analog output from cs4525 usb j8 input/output usb connection to pc for software control c2 j9 input/output connection for programming the on-board microcontroller (u3) table 1. system connections control name reference designator tactile control function master volume s1 controls settings of th e volume control register board reset s2 resets all devices in system mute s3 sets outputs of cs4525 to 50/50 duty cycle mute table 2. on-board tactile controls connector name reference designator header function dsp in j2 when shunts are placed across column 1 and 2, the cs4525 serial audio input data is sourced by the cs8416 to use external serial audio input data, connect the pcm source cable across column 2 and 3 dsp out j11 auxiliary serial audio data from the cs4525 crd4412 i/f j4 connection to crd4412a daughter card table 3. system headers
ds804rd4 15 crd4525-q1 6. crd schematics figure 6. cs4525 - schematic page 1
16 ds804rd4 crd4525-q1 figure 7. usb microcontroller & tactile control - schematic page 2
ds804rd4 17 crd4525-q1 figure 8. power & i/o connections - schematic page 3
18 ds804rd4 crd4525-q1 7. crd layout 2.9'' 4.5'' figure 9. component map
ds804rd4 19 crd4525-q1 figure 10. top-side copper layer
20 ds804rd4 crd4525-q1 figure 11. inner copper layer 1
ds804rd4 21 crd4525-q1 figure 12. inner copper layer 2
22 ds804rd4 crd4525-q1 figure 13. bottom-side copper layer
ds804rd4 23 crd4525-q1 8. performance plots unless otherwise stated, all me asurements taken utilizing digita l optical input at 1 khz. both channels were driven into 8 resistive loads, and an aes-17 20 hz to 20 khz filter was enabled during testing. -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 14. frequency response channel 1/2 channel 3/4
24 ds804rd4 crd4525-q1 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 100m 20 200m 500m 1 2 5 10 w figure 15. thd+n vs. power channel 3/4 channel 1/2
ds804rd4 25 crd4525-q1 0.001 1 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 16. thd+n vs. frequency 1w 5w 10 w
26 ds804rd4 crd4525-q1 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 17. fft at -60 db input channel 1/2 channel 3/4
ds804rd4 27 crd4525-q1 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 18. fft at 0 db input channel 3/4 channel 1/2
28 ds804rd4 crd4525-q1 -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 19. inter-mo dulation distortion of 19 khz + 20 khz channel 3/4 channel 1/2
ds804rd4 29 crd4525-q1 9. thermal de-rating the crd4525-q1 is a four-layer pcb design with 1 oz. (0.0 36 mm thick) copper. these parameters affect the ther- mal resistance and, since the pcb acts as a heat sink for the cs4525, the maximum sustained output power of the crd4525-q1. the cs4525 will gene rate heat that will flow in to the pcb and then out to the ambient air surrounding the crd4525-q1; the more outp ut power the cs4525 is delivering, the more heat it will produce. this transfer of heat is less effective at greater ambi ent temperatures. because of this, there is a function between the ambient tem- perature and the maximum sustained output power the cs4525 can deliver before heating to the point of thermal error. this function is commonly detailed in a thermal de-r ating curve, which describes how an amplifiers? rated out- put power is affected by ambient temperature. the ther mal de-rating curve of a typi cal crd4525-q1 is shown in figure 20 . figure 20. thermal de-rating curve for a typical crd4525-q1 for more information concerning thermal considerations of qfn packages, please refer to cirrus logic application note an315.
30 ds804rd4 crd4525-q1 10.electromagnetic compliance the electromagnetic interference (emi) performance of the crd4525-q1 system has been tested for electromag- netic compliance (emc) according to the fcc class b part 15 and cispr22 standards for radiated emissions. the test results show that the crd4525-q1 refere nce design complies with bot h of these standards. for optimal emi performance, all printed circuit boards (pcb?s) implementing the cs4525 device should be de- signed to match the pcb layout of the crd4525-q1 as clos ely as possible. in particular, the designer should take care to make the vp power input and pwm output filter section of the design, including component placement and trace routing, identical to that of the crd4525-q1 board. 10.1 emi testing procedures the purpose of radiated emissions testing is to ensu re that the equipment under test (eut) does not pro- duce a level of emi that would interrupt the normal op eration of other devices or systems within close prox- imity to it. to measure the emi levels, the eut and associated auxiliary equipment are placed into operation on top of a non-conductive table inside of an electr omagnetically isolated chamber, as shown in figure 21 . as the table is rotated 360, near field antennas record the am ount of noise radiating from the eut in the frequency range of 30 mhz to 1.0 ghz. these near field antennas (and associated electronics) scan and capture the emi levels at various antenna heights and orientati ons (vertical or horizontal), relative to the eut. figure 21. test facility setup the emi data from these scans are combined to create a plot of the maximum levels of noise across all antenna heights and table rotation. the plots gathered from this proc edure are called ?peak scans?. a set of peak scans (vertical and horizontal) is created for each possible operating mode, i.e. input configuration, output configuration, etc. the operating mode that produces the pe ak scans with highest levels of emi is then evaluated more closely through the gathering of quasi-peak data. quasi-peak data is gathered by m easuring the actual power content of the emi detected during the peak scan procedure. once this quasi-peak data has been recorded, it is compared against the limits of the ap- plicable emc standard to determine if the eut is in compliance with the standard. in the case of the cs4525, these limits are defined by the fcc class b part 15 and the cispr 22 emc standards. test distance eut 80 cm turntable ground plane non-conductive table coaxial cable 1 to 4 meters
ds804rd4 31 crd4525-q1 10.2 system configuration the source signal for emc testing was a 1 khz test t one generated by a battery-operated portable cd play- er. the cs4525 was driven at 1/8th of its rated power into two 8 resistive loads connected to the crd4525-q1's output connectors through 3 meters of standard speaker wire. the crd4525-q1 was pow- ered by a mean well u65s107-p2j 18 v power supply. 10.3 crd4525-q1 test results upon quasi-peak analysis of the pe ak scan data for all modes of operatio n, it has been confirmed that the crd4525-q1 complies with both the fcc class b part 15 and cispr 22 emc standards for radiated emis- sions. the peak scans for the "optical s/pd if in" mode of operation can be seen in figure 22 and figure 23 . in this mode of operation, the 1 khz test tone is supplied through an optical s/pdif signal applied to j7. it should be noted that an open frame pcb, such as the crd4525-q1, represents the worst case scenario for emc testing. systems which include a shielded chassis a nd an earth ground will produce lower levels of emi, given the same schematic and layout configuration as that of the crd4525-q1. a full com- pliance report is available upon request. figure 22. vertical peak scan data for the crd4525-q1 figure 23. horizontal peak scan data for the crd4525-q1 10.0m 100.0m 1.0g frequency (hz) 0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 amplitude (dbuv/m) vertical data limit b 10.0m 100.0m 1.0g frequency (hz) 0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 amplitude (dbuv/m) horizontal data limit b
32 ds804rd4 crd4525-q1 11.revision history release changes rd1 initial release. rd2 added section 10. ?electromagnet ic compliance? on page 30 . rd3 updated to reflect rev. b pcb design. rd4 updated to reflect rev. b pcb emc and performance results. contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest to you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. i nclusion of cirrus products in su ch applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or cus tomer?s customer uses or permits the use of ci rrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus, its o fficers, directors, employee s, distributors and other agents from any and all liability, including attorneys? fees a nd costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. windows and microsoft are registered trademarks of microsoft corporation.

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